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Temps Utile Buy files now › USD $ 5.00
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Panel for the Temps Utile 6x clock generator.
... a fairly simple breakout board for teensy 3.1/3.2, focused on clock sequencing

(the name may suggest as much ... it was stolen from M. Louis Lapicque (see: idem, 1907: Sur l'excitation par décharge de condensateurs; détermination directe de la durée et de la quantité utiles. Comptes Rendus Soc. Biol. (Paris) 62, 701-704).

hardware basics, in brief:

teensy 3.1/3.2 @ 120MHz, w/ 128x64 OLED
2 clock inputs (100k input impedance; threshold ~ 2.5V)
4 CV inputs (100k input impedance, -/+ 5V, assignable to (almost) any parameter)
6 clock outputs (5 digital, 1 DAC (12 bit): 10V (GPIO), -/+ 6V (DAC))
two encoders w/ switches; 2 tactile buttons.
14HP, ~ 25 mm Depth
firmware:

6 modes, selectable per channel:

trigger sequencer/sequence editor
clock division/multiplication
LFSR
random w/ threshold
euclidian
logic (AND, OR, XOR, NAND, NOR, XNOR)
DAC (channel #4 only): random, binary, "Turing", logistic.

Link: https://github.com/mxmxmx/temps_utile-/wiki/Temps-Utile

USD $ 5.00 Mangoest would like to share their product with the following license All Rights Reserved Read the fine print of this license Buy design files › Once purchased this file can be downloaded immediately.

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Additional info: Listed on Nov 24, 2016 Viewed 1015 times Report this item to Ponoko

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