This design is for 5 sets of transistor tiles. These sets can be used in a middle-school computer science class to demonstrate how a logic gates can be constructed from transistors.
Each tile has a laser-cut drawing of an electrical symbol (n-type or p-type transistor, power, ground) or wires on it. Students are given a schematic that they re-create using the tiles. Once complete, the students use tokens representing "0"s and "1"s to figure out which logic gate they constructed. It is assumed that the students are already familiar with the standard boolean operations (AND, OR, XOR, and NOT). [More instructions will be posted later.]
Each set of 20 tiles can be used to create an inverter (logical NOT). Two sets can be combined to construct either a NAND or a NOR gate.
Recommended material for construction: ~3mm light-colored wood